1. Field of the Invention
The present invention relates to semiconductor devices and their manufacturing method. In particular, the present invention relates to MOS transistors requiring silicide protection and their manufacturing method.
2. Description of the Background Art
In transistors used for logic LSI (large-scale integrated circuit), the reduction in the parasitic resistance of source and drain regions and the wiring resistance of a polysilicon gate electrode at the same time is effected by Salicide (self-aligned silicide) technology in which a silicide film is selectively formed in a self-aligned manner on the surfaces of a source/drain layer and a polysilicon gate electrode.
Silicide films have the advantage of reducing the parasitic resistance and wiring resistance. However, in some cases the presence of a silicide film causes an unfavorable phenomenon. To avoid such a phenomenon, the portion where formation of silicide film is not desirable is protected by a silicide protection film that prevents a silicide film formation.
The problem in forming silicide film and silicide protection film is discussed herebelow. As an example of semiconductor integrated circuits, an inverter circuit C2 and a protection circuit C1 protecting it are shown in FIG. 35.
In the protection circuit C1, a P channel MOS transistor P1 and an N channel MOS transistor N1 are connected in series and an input pad PD is connected to a node ND1 connecting the transistors P1 and N1. The gate electrode of the transistor P1 is connected to a power supply potential (Vcc) and is normally in an OFF state. The gate electrode of the transistor N1 is connected to a S ground potential and is normally in an OFF state.
In the inverter circuit C2, a P channel MOS transistor P2 and an N channel MOS transistor N2 are connected in series and a node ND2 connecting the transistors P2 and N2 is connected to another circuit (not shown). The gate electrodes of the transistors P2 and N2 are connected to the node ND1 of the protection circuit C1.
If a surge voltage is inputted through the input pad PD, i.e., an ESD (Electro Static Discharge) occurs, a voltage far higher than the operating voltages of normal MOS transistors is applied. Therefore, in the absence of the protection circuit C1, the surge voltage will be applied to the gate electrodes of the P channel MOS transistor P2 and the N channel MOS transistor N2 in the inverter circuit C2 so as to possibly cause dielectric breakdown of both the gate insulatings. However, when a surge voltage is applied, the presence of the protection circuit C1 causes a breakdown between the source and drain of the transistors P1 and N1 so that a current flows, which prevents the surge voltage from being applied to the inverter circuit C2.
However, when a very large surge voltage is applied between the source and drain in the protection circuit C1, the P channel MOS transistor P1 or the N channel MOS transistor N1 in the circuit C1 will be destroyed. A surge voltage that can destroy these channels is called an ESD resistance, and it is desirable to design its value as large as possible. If a silicide film is formed on the surface of the source and drain layer, the ESD resistance might be lowered.
FIG. 36 shows a plane construction of an MOS transistor M1. The MOS transistor M1 comprises a slender gate electrode GE provided in the center, and a source/drain layer SD on its two sides in the shorter direction, and a silicide film SF formed on the surface of the source/drain layer SD.
FIG. 37 is an enlarged view of the area A of FIG. 36. Generally, the silicide film SF is of polycristal construction and comprises large and small silicide crystal grains GR, as shown in FIG. 37. Accordingly, each grain shape is reflected in the grain boundaries to exhibit corrugations. This is true for the edge portion of the silicide film SF along with the edge portion of the gate electrode GE. As shown in FIG. 37, crystal grains GR face one another across the gate electrode GE. When a surge voltage is applied to such a structure, the surge current is concentrated between the projections (i.e., the space indicated by two arrows in opposite directions) of the crystal grains GR on both sides of the gate electrode GE and, in such portions, the intensive breakage occurs. This makes the MOS transistor inoperative, failing to function as a protection circuit. For this reason, silicide film is not formed on the surface of the source/drain layer in the protection circuit, and a silicide protection film is formed instead.
With reference to FIG. 38, the construction of an MOS transistor M2 with a silicide protection film is described herebelow.
As shown in FIG. 38, a silicide protection film SP comprising a silicon oxide film (SiO2) is formed on the surfaces of a gate electrode GE and of a source/drain layer SD in the vicinity of the gate electrode GE while no silicide film SF is formed over the silicide protection film SP. This construction allows to increase the distance between the edge of the silicide film SF and the edge of the gate electrode GE. Even if the edge of the silicide film SF is in the shape of a continuous corrugation and hence a surge voltage tends to concentrate on projected portions, the surge current will be dispersed because it must pass a long distance through a lightly doped drain region (not shown) and a source/drain layer. Furthermore, when the surge current passes through the lightly doped drain region having a relatively high resistance, a voltage drop and the like occur and thus prevents the MOS transistor from being damaged.
As described above, the silicide protection film SP has been used to protect a silicide film SF formation in MOS transistors in which its formation can cause disadvantages.
In the formation of a silicide protection film SP, a silicon oxide film is formed over the entire surface of a silicon substrate SB-and the silicon oxide film is then selectively removed by dry etching, such as RIE (Reactive Ion Etching), to form the silicide protection film SP only on the surfaces of a gate electrode GE and of a source/drain layer SD in the vicinity of the gate electrode GE.
Referring to FIGS. 39 and 40 that are a cross-sectional view of a MOS transistor at a processing step subsequent to the silicide protection film SP formation, the problems resulting from the formation of the silicide protection film are discussed next.
With reference to FIG. 39, over an SOI substrate SI, there is a protection region PR in which a plurality of MOS transistors M1 requiring a silicide protection film will be formed and there is also a normal region OR in which a plurality of MOS transistors M2 requiring no silicide protection film will be formed. The SOI substrate SI comprises a silicon substrate SB, a buried insulating layer BO, and an SOI layer SL, which are formed in this order on the substrate SB.
In the normal region OR, a silicide film SF is formed over a source/drain layer SD2 and a gate electrode GE2, whereas in the protection region PR a silicide protection film SP of oxide film is formed over the entire surface and there is no silicide film SF over a source/drain layer SDI and a gate electrode GE1.
After forming the silicide film SF and the silicide protection film SP, an interlayer insulating film IZ is formed over the SOI substrate SI. Thereafter, as shown in FIG. 40, contact holes CH1 and CH2 are formed so as to extend through the interlayer insulating film IZ to reach the source/drain layers SD1 and SD2, respectively.
The problem at this time is that the selective ratio of etching differs between the silicide film SF and the silicide protection film SP. That is, since the silicide protection film SP is an oxide film and is more easily etched than the silicide film SF, if the contact holes CH1 and CH2 are formed at the same time, the contact hole CH1 results in somewhat over-etching, or in some cases it extends through the SOI layer to reach the buried insulating layer BO, failing to function as an MOS transistor.
As described earlier, to avoid the breakdown of MOS transistors by a surge voltage, a voltage drop due to a high resistance layer, e.g., a lightly doped drain layer; is effective. However, almost all parts beneath the silicide protection 20 film SP are occupied by the source/drain layer and even the source/drain layer SD1 on which no silicide film SF is present has a sheet resistance of about several hundred xcexa9/xe2x96xa1. In order to expect a voltage drop in surge voltage, it is therefore necessary to form a source/drain layer SD1 that is covered with a silicide protection film SP over a wide area. This is negative toward device downsizing.
According to a first aspect of the present invention, a semiconductor device comprising an MOS transistor formed on a semiconductor substrate is characterized in that: the MOS transistor comprises at least one silicide protection structure for preventing a silicide film formation in a predetermined portion on a surface of an active region outward side faces of a gate electrode; a first semiconductor layer of a first concentration is provided in a surface of the semiconductor substrate beneath the aforementioned at least one silicide protection structure; a second semiconductor layer of a second concentration is provided in a surface of the semiconductor substrate excluding a portion in which the aforementioned at least one silicide protection structure is formed; the silicide film is provided on the second semiconductor layer; the second semiconductor layer is a source/drain layer of the MOS transistor; and the first concentration is lower than the second concentration.
According to a second aspect of the present invention, at least one silicide protection structure is composed of an insulating film; and the first semiconductor layer is a semiconductor layer of a conductivity type opposite to that of the source/drain layer.
According to a third aspect of the present invention, at least one silicide protection structure is composed of an insulating film; and the first semiconductor layer is a semiconductor layer having a conductivity type identical to that of the source/drain layer.
According to a fourth aspect of the present invention, a field shield gate electrode defining the active region and electrically isolating the MOS transistor from other semiconductor elements, is provided on the semiconductor substrate. The field shield gate electrode has a field shield insulating film, a conductor layer, and a conductor layer, upper insulating film, which are laminated in this order on the semiconductor substrate. A sidewall insulating film is provided on side faces of the field shield insulating film, the conductor layer, and the conductor layer upper insulating film. The insulating film of the aforementioned at least one silicide protection structure and the sidewall insulating film are formed simultaneously with an identical material.
According to a fifth aspect of the present invention, a field shield gate electrode defining the active region and electrically isolating the MOS transistor from other semiconductor elements, is provided on the semiconductor substrate. The field shield gate electrode has a field shield insulating film, a conductor layer, and a conductor layer upper insulating film, which are laminated in this order on the semiconductor substrate. The aforementioned at least one silicide protection structure and the field shield gate electrode are formed simultaneously with an identical material; and the first semiconductor layer is a semiconductor layer having a conductivity type identical to that that of the source/drain layer of the MOS transistor.
According to a sixth aspect of the present invention, at least one silicide protection structure and the gate electrode of the MOS transistor are formed simultaneously with an identical construction; and the first semiconductor layer is a semiconductor layer having a conductivity type identical with that of the source/drain layer of the MOS transistor.
According to a seventh aspect of the present invention, at least one silicide protection structure partially includes at least one opening portion whose bottom is composed of the silicide film; and the second semiconductor layer is provided on a surface of the active region beneath the silicide film of the aforementioned at least one opening portion.
According to an eighth aspect of the present invention, at least one silicide protection structure is in a slender shape in plan view. A plurality of opening portions are arranged in a row in a longitudinal direction of the aforementioned at least one silicide protection structure. A longitudinal direction of the aforementioned at least one silicide protection structure is parallel to a longitudinal direction of the gate electrode.
According to a ninth aspect of the present invention, the device includes a plurality of silicide protection structures; and the plurality of opening portions are arranged at an interval so that they are in parallel to a longitudinal direction of the gate electrode.
According to a tenth aspect of the present invention, the device includes a plurality of silicide protection structures and each shape in plan view is approximately a rectangle. The device includes only one opening portion; and the plurality of silicide protection structures are arranged at least in parallel to a longitudinal direction of the gate electrode.
According to an eleventh aspect of the present invention, the plurality of silicide protection structures are arranged in a longitudinal direction of the gate electrode and in a direction vertical to the longitudinal direction of the gate electrode.
According to a twelfth aspect of the present invention, at least one silicide protection structure has an approximately rectangular shape in plan view; the device includes a plurality of opening portions; and the plurality of opening portions are arranged in a direction parallel to a longitudinal direction of the gate electrode and in a direction vertical to the longitudinal direction of the gate electrode.
According to a thirteenth aspect of the present invention, a manufacturing method of a semiconductor device comprising a field shield gate electrode that defines an MOS transistor formed on a semiconductor substrate and an active region outward of side faces of a gate electrode of the MOS transistor and isolates electrically the MOS transistor from other semiconductor elements, comprises the steps of: (a) selectively forming a first semiconductor layer of a first concentration in a predetermined portion of the semiconductor substrate; (b) to define the active region, selectively laminating a field shield insulating film, a conductor layer and a conductor layer upper insulating film on the semiconductor substrate, to form the field shield gate electrode, and selectively forming a silicide protection structure having an identical construction as the field shield gate electrode on the first semiconductor layer; (c) forming the gate electrode on the semiconductor substrate and performing an ion implantation of impurity by using the field shield gate electrode, the silicide protection structure, and the gate electrode, as masks, to form a second semiconductor layer of a second concentration within the semiconductor substrate; and (d) forming a silicide film in a self aligned manner on the second semiconductor layer by a salicide process, wherein the first concentration is lower than the second concentration; the second semiconductor layer is formed as a source/drain layer of the MOS transistor; and the first semiconductor layer is formed so that it has a conductivity type identical with that of the source/drain layer.
According to a fourteenth aspect of the present invention, the step (b) includes the step of forming the silicide protection structure so as to have an opening portion, at a bottom of which the first semiconductor layer is exposed; the method further comprising the step, prior to the step (c), of forming a sidewall insulating film on side faces of the silicide protection structure and the field shield gate electrode; wherein the sidewall insulating film is also formed on side faces of the conductor layer in the opening portion; and the step (c) includes the step of forming the second semiconductor layer within the first semiconductor layer of the opening portion bottom.
According to a fifteenth aspect of the present invention, a manufacturing method of a semiconductor device having an MOS transistor formed on a semiconductor substrate, comprises the steps of: (a) selectively forming a first semiconductor layer of a first concentration in a predetermined portion of the semiconductor substrate; (b) selectively laminating a gate insulating film and a conductor layer in this order on the semiconductor substrate to form a gate electrode of the MOS transistor, and selectively forming a silicide protection structure having an identical construction as the gate electrode on the first semiconductor layer; (c) performing an ion implantation of impurity by using the silicide protection structure and the gate electrode, as masks, to form a second semiconductor layer of a second concentration in the semiconductor substrate; and(d) forming a silicide film in a self-aligned manner on the second semiconductor layer by a salicide process, wherein the first concentration is lower than the second concentration; the second semiconductor layer is formed as a source/drain layer of the MOS transistor; and the first semiconductor layer has a conductivity type identical with that of the source/drain layer.
According to a sixteenth aspect of the present invention, the step (b) includes the step of forming the silicide protection structure so as to have an opening portion, at a bottom of which the first semiconductor layer is exposed; the method comprising the step, prior to the step (c), of forming a sidewall insulating film on side faces of the silicide protection structure and the gate electrode; wherein the sidewall insulating film is also formed on side faces of the conductor layer in the opening portion; and the step (c) includes the step of forming the second semiconductor layer in the first semiconductor layer of the opening portion bottom.
According to a seventeenth aspect of the present invention, the method further comprises the step of (e) forming a contact hole extending through the silicide protection structure to reach into the first semiconductor layer.
In the semiconductor device of the first aspect of the present invention, no silicide film is present on the first semiconductor layer beneath the silicide protection structure and the first semiconductor layer has a concentration lower than that of the source/drain layer, resulting in an electrically high resistance region. Thus, when a surge voltage is applied between the source and drain, a voltage drop due to the first semiconductor layer prevents the destroy of the MOS transistor. Additionally, by making the first semiconductor layer have a sheet resistance in k xcexa9 unit, it is able to lessen the area required in lowering the surge voltage. Furthermore, the presence of the silicide film over the source/drain layer facilitates the decision of etching end point when forming a contact hole over the source/drain layer, preventing the over-etching of the source/drain layer.
In the semiconductor device of the second aspect of the present invention, since the first semiconductor layer is a semiconductor layer of a conductivity type opposite to that of the source/drain layer of the MOS transistor, a PN junction is formed with the source and drain layer to produce a region of electrically very high resistance.
In the semiconductor device of the third aspect of the present invention, since the first semiconductor layer is a semiconductor layer of a conductivity type identical to that of the source/drain layer of the MOS transistor, the resultant high resistance region has a lower resistance value as compared to cases where a PN junction is formed.
In the semiconductor device of the fourth aspect of the present invention, the insulating film of the silicide protection structure and the sidewall insulating film are formed simultaneously using the same material, requiring no etching step for forming the silicide protection structure only. Therefore, if a semiconductor substrate is, for example, an SOI substrate, the damage due to etching cannot be ignored because SOI layers are generally thin, however, no etching is needed in forming the silicide protection structure and thus avoids increasing the damage by etching the SOI layer.
In the semiconductor device of the fifth aspect of the present invention, the silicide protection structure and the field shield gate are formed simultaneously with the same construction, requiring no steps for forming the silicide protection structure only, e.g., etching. Therefore, if the semiconductor substrate is, for example, an SOI substrate, the damage due to etching cannot be ignored because SOI layers are generally thin, however, no additional steps, e.g., etching, for forming the silicide protection structure are required and thus avoids increasing damage by etching the SOI layer.
In the semiconductor device of the sixth aspect of the present invention, the silicide protection structure and the gate electrode are formed simultaneously with the same construction, requiring no steps for forming the silicide protection structure only, e.g., etching. If the semiconductor substrate is for example an SOI substrate, the damage due to etching cannot be ignored because SOI layers are generally thin, however, no additional steps, e.g., etching, for forming the silicide protection structure are required and thus avoids increasing damage by etching the SOI layer. In addition, since the gate electrode structure is utilized as a silicide protection structure, the silicide protection structure can be formed even in semiconductor devices without a special construction, such as the field-shield isolation structure, thereby leading to a wide applicability of the present invention.
In the semiconductor device of the seventh aspect of the present invention, a contact hole can be provided over at least one opening portion of at least one silicide protection structure. It is therefore unnecessary to provide the space for forming a contact hole over the source/drain layer. This construction is well suited for applications in which the size of an active region is limited.
In the semiconductor device of the eighth aspect of the present invention, a uniform flow of surge current can be obtained by adjusting the silicide protection structure to have the length of the gate electrode and by arranging the opening portions in a row in the longitudinal direction of the silicide protection structure.
In the semiconductor device of the ninth aspect of the present invention, since a plurality of silicide protection structures have the opening portions arranged in a row, respectively, the resistance value of the source/drain layer can be changed by modifying the opening portion in which a contact hole will be formed.
In the semiconductor device of the tenth aspect of the present invention, the presence of the silicide film between the silicide protection structures increases the area of the region of the silicide film, thus lowering the resistance value of the source/drain layer.
In the semiconductor device of the eleventh aspect of the present invention, the modification of the opening portion in which a contact hole will be formed enables to change the resistance value of the source/drain layer, and, since the silicide film is formed between the silicide protection structures, the area of the region of the silicide film is increased and thus lowers the resistance value of the source/drain layer.
In the semiconductor device of the twelfth aspect of the present invention, the modification of the opening portion in which a contact hole will be formed enables to change the resistance value of the source/drain layer, and, since the area of the region of the silicide film is reduced, the resistance value of the source/drain layer is increased.
The manufacturing method of the thirteenth aspect of the present invention provides a manufacturing method suited for the semiconductor device in accordance with the fifth aspect.
The manufacturing method of the fourteenth aspect of the present invention provides a manufacturing method suited for the semiconductor device in accordance with the seventh aspect.
The manufacturing method of the fifteenth aspect of the present invention provides a manufacturing method suited for the semiconductor device in accordance with the sixth aspect.
The manufacturing method of the sixteenth aspect of the present invention provide a manufacturing method suited for the semiconductor device in accordance with the seventh aspect.
In the manufacturing method of the seventeenth aspect of the present invention, the feature that the contact hole extends through the silicide protection structure to reach into the first semiconductor layer increases the alignment margin in forming a contact hole as compared to cases where an opening portion is formed in a silicide protection structure and a contact hole is formed therein. This simplifies the processing steps and suppresses the disadvantage associated with the positional drift of the contact hole, preventing a drop in yield. In addition, if the contact hole is filled with a conductor, the conductor is electrically connected to a conductor layer of the silicide protection structure to cause a parasite capacity between the conductor layer and a wiring layer, such as a gate wiring layer. As a result, a CR circuit is formed by the parasite capacity and the resistance components in the first semiconductor layer. When a sudden input of, such as a surge voltage, is applied, the surge voltage is reduced by the CR circuit to improve the protection capability of the MOS transistor to ESD.
An object of the present invention is to provide a semiconductor device with a silicide protection structure that prevents the over-etching of a source/drain layer in forming contact holes and permits a voltage drop of surge voltage without increasing the area of a source/drain layer, as well as a manufacturing method of the semiconductor device.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.